1. Field of the Invention
The present invention is related to radiation hardened integrated circuits and, more particularly, to clock generation circuits for radiation hardened integrated circuits.
2. Related Art
Increasingly, space-based communication systems are including integrated circuits (IC) made in advanced deep sub-micron Field Effect Transistor (FET) technology. Typically, these ICs are in the insulated gate silicon technology commonly referred to as complementary metal oxide semiconductor (CMOS). CMOS ICs are advantageous in that they are high speed and low power. The CMOS ICs use little power compared to what other technologies require for comparable speed and function.
In a space-based environment, however, ionic strikes by sub-atomic cosmic particles are known to introduce circuit disturbances. These circuit disturbances are known as single event effects (SEEs), and as single event upsets (SEUs) when corrupting data in storage elements. Radiation hardened latches are well known and are used, effectively, to reduce or to eliminate SEUs in space-based IC registers, latches and other storage elements. These radiation hardened storage elements are designed to protect from disturbance what is stored in them in spite of any cosmic particle hits that the storage elements might sustain.
However, over time, as circuit performance has increased, the propagation delay through circuit logic between the radiation hardened latches or registers has been reduced to within an order of magnitude of the duration of an SEE. For example, a pipelined logic chip operating at 200 MHz can have 3-3.5 nanoseconds allocated for logic propagation delays between registers. A single event upset occurring in the logic can cause an invalid result for 0.5-1.0 nanoseconds which is a significant amount of time with respect to a pulse width. Such an event occurring in a clock distribution chain can cause a more widespread and potentially a much more serious result.
Typically, IC clock signals are received by a receiver connected to a bonding pad of the IC. The receiver inverts and redrives the clock signal, typically, to multiple locations on the IC. At each of these locations, the clock signal is again inverted and redriven. This reinverted clock signal can be further distributed to multiple locations, where it can again be reinverted and redriven. The clock distribution can be represented as a tree spreading out from the original receiver.
The effects from an event occurring in a clock tree can cause a transient effect in the clock signal on part of the clock tree for approximately 0.5 nanoseconds, which can appear as a false clock pulse. Further, the number of latches and registers affected by the false clock pulse is random and depends on where in the tree the event occurs. Such a false clock pulse can clock registers causing the registers to latch invalid data. The invalid latched data can be passed from the initial registers through the next logic stage. This can result in multiple uncorrectable multi-bit logic errors.
The severity of this problem only increases with greater levels of very large scale integration (VLSI) circuit integration because these higher levels of integration achieve higher performance through smaller features. For example, with circuits operating in the 1 GHz clock range, a single event could wipe out an entire clock cycle for the affected part of the IC logic. Thus, it can be seen that clock tree SEE immunity is critical to preventing logic errors.
For example, FIG. 6 illustrates a typical state of the art scan d-flip-flop (scan dff) 600. The scan d flip-flop 600 includes a 2:1 multiplexer 602, which is coupled to a first level sensitive latch 604. The first level sensitive latch 604 is coupled to a second level sensitive latch 606. The scan dff 600 is clocked by a clock signal 607. The clock signal 607 is split into complementary signals by inverting clock signal 607 with inverter 608. The complementary clock signals are provided to first level sensitive latch 604 and second level sensitive latch 606, gating first and second pairs of pass gates 610, 612 and 614, 616, respectively.
When selected, an input DATAIN 618 passes through the 2:1 multiplexer 602 to the first pair of pass gates 610, 612 as complementary outputs 620, 622 of multiplexer 602. When the clock signal 607 is low, pass gates 610, 612, are turned on so that data and complementary outputs 620, 622 are passed to first level sensitive latch 604 and are stored therein temporarily. With the clock signal 607 low, the second pair of pass gates 614, 616 turn off contemporaneously, and isolate the second level sensitive latch 606 from outputs 624, 626 of the first level sensitive latch 604.
The rising edge of clock signal 607 turns on the second pair of pass gates 614, 616 as the output of inverter 608 falls, simultaneously, to turn off the first pair of pass gates 610, 612. When the first pair of pass gates 610, 612 is turned off, the complementary outputs 620, 622 are isolated from the first level sensitive latch 604 and, so, data is latched in the first level sensitive latch 604. When the second pair of pass gates 614, 616 is turned on, outputs 624, 626 of the first level sensitive latch 604 are passed to the second level sensitive latch 606. The state of outputs 624, 626, is stored, temporarily, in the second level sensitive latch 606 and, simultaneously, is passed out on an output DATAOUT 628. When clock signal 607 falls, on the next clock cycle, the second pair of pass gates 614, 616 is turned off, isolating the second level sensitive latch 606 from the outputs 604, 626 of first level sensitive latch 604, latching data in the second level sensitive latch 606 to complete the clock cycle.
Normally, when the clock signal 607 is well behaved with regularly spaced high and low periods, it is sufficient that data provided to the input DATAIN 618 meet setup (i.e., be valid for a specified period prior to the rise of clock signal 607) and hold (i.e., remain valid for a specified period after the rise of clock signal 607) timing requirements. At any time other than this window around clock signal 607 rising, the state of input DATAIN 618 is specified as a xe2x80x9cdon""t carexe2x80x9d condition.
Unfortunately, an upsetting event occurring in the clock tree prior to clock signal 607 can cause a false clock pulse on clock signal 607. Since input DATAIN 618 is specified as a xe2x80x9cdon""t care,xe2x80x9d a falling edge of a false clock pulse on clock signal 607 could cause the first level sensitive latch 604 to switch states, inadvertently storing data. Further, when the input clock returns high, that invalid level can be passed to the second level sensitive latch 606 and out of the scan dff 600 on output DATAOUT 128. The false clock pulse is a pulse perturbed by an SEE.
Conventional clock splitters have shortcomings. With regard to high performance circuit designs, it is desirable that SEU tolerant complementary clock signals be provided for clocking level sensitive scan design (LSSD) latches. It is also desirable that clock signals be provided that could be configured to permit controlling or managing clock skew.
Thus, for reasons stated above, and for other reasons stated below which will become apparent to those skilled in the relevant art upon reading and understanding the present specification, what is needed are clock generation circuits with reduced SEE sensitivity which could provide for improved manageability of clock skew.
The above mentioned problems with clock generation circuits and radiation hardened storage elements and other problems are addressed by the present invention and which will be understood by reading and studying the following specification.
In an exemplary embodiment of the present invention, a clock splitter circuit is disclosed including a first leg including a first and-or-inverter (AOI) circuit having a first input coupled to an overlap_enable signal, a second input coupled to an inverted overlap_enable signal, a third input coupled to an inverted first clock input signal, and a fourth input coupled to a second clock input signal that is substantially 180 degrees out of phase with the first clock input signal, a first asymmetric variable delay (AVD) circuit having an input coupled to an output of the first AOI circuit, and having an input coupled to a waitr_signal, a first tri-state inverter circuit having a first input coupled to an output of the first AVD circuit, and a second input coupled to the inverted first clock input signal, and an output coupled to a first clock output signal; and a second leg including a second and-or-inverter (AOI) circuit having a first input coupled to the overlap_enable signal, a second input coupled to the inverted overlap_enable signal, a third input coupled to an inverted second clock input signal, and a fourth input coupled to a first clock input signal that is substantially 180 degrees out of phase with the second clock input signal, a second AVD circuit having an input coupled to an output of the second AOI circuit, and having an input coupled to the waitr_signal, a second tri-state inverter circuit having a first input coupled to an output of the second AVD circuit, and a second input coupled to the inverted second clock input signal, and an output coupled to a second clock output signal.
In an exemplary embodiment of the present invention, the first clock input signal and the second clock input signal are complementary clock signals.
In an exemplary embodiment of the present invention, the first AVD circuit includes first, second and third inverters coupled in series, where an input to the first inverter is coupled to the first output of the first AOI circuit and where an output of the first inverter is coupled to an input of the second inverter, and where an output of the second inverter is coupled to an input of the third inverter, where an output of the third inverter is the first AVD output signal. In an exemplary embodiment of the present invention, the first AVD circuit also includes first and second series coupled NFETs, where a drain-source region of the second NFET is coupled to ground, where a source-drain region of the first NFET is coupled to the output of the second inverter, where a gate of the first NFET is gated by the output of the first inverter, and where a gate of the second NFET is gated by the waitr_signal.
In an exemplary embodiment of the present invention, where the first AOI circuit includes a NOR gate having an output coupled to the first output of the first AOI circuit, and first and second AND gates each having an output coupled to separate inputs of the NOR gate, where the first AND gate has a first input coupled to the overlap_enable signal, and a second input coupled to the inverted first clock input signal, and where the second AND gate has a first input coupled to the inverted overlap_enable signal, and a second input coupled to the second clock input signal.
In an exemplary embodiment of the present invention, the first tri-state inverter circuit includes first and second PFETs coupled in series, where a source-drain region of the first PFET is coupled to a VDD signal, a gate of the first PFET is gated by the inverted first clock input signal, and a gate of the second PFET is gated by the first output of the first AVD circuit, first and second NFETs coupled in series, coupled at a source-drain region of the first NFET to the output of the first tri-state inverter, and to a drain-source region of the second PFET, where a drain-source region of the second NFET is coupled to ground, and a gate of the second NFET is gated by the inverted first clock input signal, and a gate of the first NFET is gated by the first output of the first AVD circuit.
In an exemplary embodiment of the present invention, a clock splitter circuit for providing a radiation hardened pair of adjustably non-overlapping complementary clocks is disclosed, the clock splitter circuit including a pair of clock inverter legs, each clock inverter leg including AOI means for logically ANDing, ORing, and Inverting (AOI) a first input coupled to an overlap_enable signal, a second input coupled to an inverted overlap_enable signal, a third input coupled to an inverted first clock input signal, and a fourth input coupled to an second clock input signal that is substantially 180 degrees out of phase with the first clock input signal, asymmetric variable delay (AVD) means for delaying and adjusting a non-overlap breadth having an input responsive to a first output of the AOI means, and having an input coupled to a waitr_enable signal, tri-state means for inverting responsive to an output of the first AVD means, and responsive to the inverted first clock input signal, and generating a first clock output signal.
In an exemplary embodiment of the present invention, the AVD means includes first, second and third means for inverting coupled in series where the first means is responsive to the output of the first AOI means, where the second means is responsive to an output of the first means, where the third means is responsive to an output of the second means, and where the third means generates the first AVD circuit output signal, and first and second series coupled NFETs, where a source-drain region of the first NFET is coupled to the output of the second inverting means, where a gate of the first NFET is gated by the output of the first inverting means, and where a gate of the second NFET is gated by the waitr_signal, where a drain-source region of the second NFET is coupled to ground.
In an exemplary embodiment of the present invention, the AOI means includes first and second AND logic means for ANDing, where the first AND logic means is responsive to the overlap_enable signal, and is responsive to the inverted first clock input signal, and where the second AND logic means is responsive to the inverted overlap_enable signal, and is responsive to the second clock input signal, and NOR logic means for NORing responsive to the first and the second AND logic means and generating the first output of the AOI circuit.
It is an advantage of the present invention that integrated circuit chip SEE sensitivity can be reduced.
It is a further advantage of the present invention that pulse rejection can be provided.
It is a further advantage of the present invention that non-overlap can be controlled.
It is a further advantage of the present invention that clock skew can be controlled.
It is another advantage of the present invention that integrated circuit power can be reduced.
It is yet another advantage of the present invention that integrated circuit chip clock tree SEE sensitivity can be reduced.
It is yet another advantage of the present invention that timing related SEU sensitivity is reduced on space-based integrated circuit chips.
Further features and advantages of the invention, as well as the structure and operation of various embodiments of the invention, are described in detail below with reference to the accompanying drawings. In the drawings, like reference numbers generally indicate identical, functionally similar, and/or structurally similar elements. The drawing in which an element first appears is indicated by the leftmost digits in the corresponding reference number.